Sciweavers

2945 search results - page 36 / 589
» Designing and Implementing Malicious Hardware
Sort
View
FPGA
2007
ACM
122views FPGA» more  FPGA 2007»
15 years 10 months ago
The shunt: an FPGA-based accelerator for network intrusion prevention
Today’s network intrusion prevention systems (IPSs) must perform increasingly sophisticated analysis—parsing protocols and interpreting application dialogs rather than simply ...
Nicholas Weaver, Vern Paxson, José M. Gonz&...
ASAP
2007
IEEE
104views Hardware» more  ASAP 2007»
15 years 5 months ago
Hardware Acceleration for 3-D Radiation Dose Calculation
Abstract— The problem of calculating accurate dose distributions lies in the heart of modern radiation therapy for cancer treatment. Software implementations of dose calculation ...
Bo Zhou, Xiaobo Sharon Hu, Danny Z. Chen, Cedric X...
SIGCOMM
2010
ACM
15 years 4 months ago
Fived: a service-based architecture implementation to innovate at the endpoints
Security functions such as access control, encryption and authentication are typically left up to applications on the modern Internet. There is no unified system to implement thes...
D. J. Capelis, Darrell D. E. Long
GLVLSI
2002
IEEE
127views VLSI» more  GLVLSI 2002»
15 years 9 months ago
A new look at hardware maze routing
This paper describes a new design for a hardware accelerator to support grid-based Maze Routing. Based on the direct mapped approach of Breuer and Shamsa [3], this work refines th...
John A. Nestor
ICCD
2006
IEEE
107views Hardware» more  ICCD 2006»
16 years 28 days ago
Design and Implementation of the TRIPS Primary Memory System
Abstract— In this paper, we describe the design and implementation of the primary memory system of the TRIPS processor. To match the aggressive execution bandwidth and support hi...
Simha Sethumadhavan, Robert G. McDonald, Rajagopal...