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FPL
2009
Springer
96views Hardware» more  FPL 2009»
15 years 11 months ago
Noise impact of single-event upsets on an FPGA-based digital filter
Field-programmable gate arrays are well-suited to DSP and digital communications applications. SRAM-based FPGAs, however, are susceptible to radiation-induced single-event upsets ...
Brian H. Pratt, Michael J. Wirthlin, Michael P. Ca...
ATS
2000
IEEE
98views Hardware» more  ATS 2000»
15 years 10 months ago
Embedded core testing using genetic algorithms
Testing of embedded cores is very difficult in SOC (system-on-a-chip), since the core user may not know the gate level implementation of the core, and the controllability and obse...
Ruofan Xu, Michael S. Hsiao
DATE
2000
IEEE
108views Hardware» more  DATE 2000»
15 years 10 months ago
A 50 Mbit/s Iterative Turbo-Decoder
Very low bit error rate has become an important constraint in high performance communication systems that operate at very low signal to noise ratios: due to their impressive codin...
F. Viglione, Guido Masera, Gianluca Piccinini, Mas...
ECBS
2000
IEEE
155views Hardware» more  ECBS 2000»
15 years 10 months ago
A Component-Driven Architecture for Internet-Based, Directly Reactive Information Systems
In this paper we focus on the architecture-based development of what we call directly reactive information systems on the Internet. These systems exhibit full content management o...
René Stolle, Wilhelm Rossak, Vassilka Kirov...
ICECCS
2000
IEEE
133views Hardware» more  ICECCS 2000»
15 years 10 months ago
An Analysis Tool for Coupling-Based Integration Testing
This research is part of a project to develop practical, effective, formalizable, automatable techniques for integration testing. Integration testing is an important part of the t...
A. Jefferson Offutt, Aynur Abdurazik, Roger T. Ale...