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» Designing and Implementing Malicious Hardware
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IEEEPACT
2006
IEEE
16 years 5 days ago
Branch predictor guided instruction decoding
Fast instruction decoding is a challenge for the design of CISC microprocessors. A well-known solution to overcome this problem is using a trace cache. It stores and fetches alrea...
Oliverio J. Santana, Ayose Falcón, Alex Ram...
154
Voted
IPPS
2006
IEEE
16 years 5 days ago
Accelerating DTI tractography using FPGAs
Diffusion Tensor Imaging (DTI) tractography in Magnetic Resonance Imaging (MRI) is a computationally intensive procedure, requiring on the order of tens of minutes to complete tr...
Kwatra Kwatra, Viktor K. Prasanna, Mitali Singh
ISCAS
2006
IEEE
162views Hardware» more  ISCAS 2006»
16 years 5 days ago
Combined image signal processing for CMOS image sensors
This paper presents an efficient image signal processing structure for CMOS image sensors to achieve low area and power consumption. Although CMOS image sensors (CISs) have variou...
Kimo Kim, In-Cheol Park
ISCAS
2005
IEEE
167views Hardware» more  ISCAS 2005»
15 years 11 months ago
Low-power log-MAP turbo decoding based on reduced metric memory access
Due to the powerful error correcting performance, turbo codes have been adopted in many wireless communication standards. Although several low-power techniques have been proposed,...
Dong-Soo Lee, In-Cheol Park
146
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MSS
2005
IEEE
106views Hardware» more  MSS 2005»
15 years 11 months ago
An Architecture for Lifecycle Management in Very Large File Systems
We present a policy-based architecture STEPS for lifecycle management (LCM) in a mass scale distributed file system. The STEPS architecture is designed in the context of IBM’s ...
Akshat Verma, David Pease, Upendra Sharma, Marc Ka...