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DATE
2007
IEEE
156views Hardware» more  DATE 2007»
16 years 9 days ago
Process variation tolerant low power DCT architecture
: 2-D Discrete Cosine Transform (DCT) is widely used as the core of digital image and video compression. In this paper, we present a novel DCT architecture that allows aggressive v...
Nilanjan Banerjee, Georgios Karakonstantis, Kaushi...
ISCA
2007
IEEE
177views Hardware» more  ISCA 2007»
16 years 8 days ago
Adaptive insertion policies for high performance caching
The commonly used LRU replacement policy is susceptible to thrashing for memory-intensive workloads that have a working set greater than the available cache size. For such applica...
Moinuddin K. Qureshi, Aamer Jaleel, Yale N. Patt, ...
MOBIQUITOUS
2007
IEEE
16 years 7 days ago
Battery-Aware Embedded GPS Receiver Node
—This paper discusses the design and implementation of an ultra low power embedded GPS receiver node for use in remote monitoring situations where battery life is of the utmost i...
Dejan Raskovic, David Giessel
FPGA
2007
ACM
163views FPGA» more  FPGA 2007»
16 years 4 days ago
Improved SAT-based Boolean matching using implicants for LUT-based FPGAs
Boolean matching (BM) is a widely used technique in FPGA resynthesis and architecture evaluation. In this paper we present several improvements to the recently proposed SAT-based ...
Jason Cong, Kirill Minkovich
IESS
2007
Springer
120views Hardware» more  IESS 2007»
16 years 3 days ago
Error Containment in the Time-Triggered System-On-a-Chip Architecture
Abstract: The time-triggered System-on-a-Chip (SoC) architecture provides a generic multicore system platform for a family of composable and dependable giga-scale SoCs. It supports...
Roman Obermaisser, Hermann Kopetz, Christian El Sa...