2945 search results - page 77 / 589 » Designing and Implementing Malicious Hardware |
160
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ICIP
2006
IEEE
16 years 6 months ago
2006
IEEE
We present in this paper a method for implementing moment functions in a CMOS retina for shape recognition applications. The method is based on the use of binary patterns and it a...
122
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ERSA
2007
15 years 5 months ago
2007
Molecular Dynamics simulations have become an interesting target for acceleration using Field-Programmable Gate Arrays (FPGA). Still to be attempted completely in FPGA hardware is...
190
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CC
2008
Springer
15 years 6 months ago
2008
Springer
JIT compilation is a model of execution which translates at run time critical parts of the program to a low level representation. Typically a JIT compiler produces machine code fro...
124
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FPL
2007
Springer
15 years 10 months ago
2007
Springer
This paper describes an execution cache that uses process migration between hardware and software contexts by way of run-time reconfiguration (RTR) of Field Programmable Gate Arr...
121
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ISPD
2006
ACM
15 years 10 months ago
2006
ACM
APlace is a high quality, scalable analytical placer. This paper describes our recent efforts to improve APlace for speed and scalability. We explore various wirelength and densi...