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SIGGRAPH
1999
ACM
15 years 8 months ago
A Real-Time Low-Latency Hardware Light-Field Renderer
This paper describes the design and implementation of an architecture for interactively viewing static light fields with very low latency. The system was deliberately over enginee...
Matthew J. P. Regan, Gavin S. P. Miller, Steven M....
IJCSS
2007
133views more  IJCSS 2007»
15 years 4 months ago
Synthesis of Read-Once Digital Hardware with Reduced Energy Delay Product
This paper presents a low power driven synthesis framework for the unique class of nonregenerative Boolean Read-Once Functions (BROF). A two-pronged approach is adopted, where the...
P. Balasubramanian, S. Theja
JRTIP
2007
108views more  JRTIP 2007»
15 years 4 months ago
Real-time hardware acceleration of the trace transform
The trace transform is a novel algorithm that has been shown to be effective in a number of image recognition tasks. It is a generalisation of the Radon transform that has been wid...
Suhaib A. Fahmy, Christos-Savvas Bouganis, Peter Y...
CHES
2005
Springer
155views Cryptology» more  CHES 2005»
15 years 10 months ago
Scalable Hardware for Sparse Systems of Linear Equations, with Applications to Integer Factorization
Motivated by the goal of factoring large integers using the Number Field Sieve, several special-purpose hardware designs have been recently proposed for solving large sparse system...
Willi Geiselmann, Adi Shamir, Rainer Steinwandt, E...
ISSS
2000
IEEE
290views Hardware» more  ISSS 2000»
15 years 8 months ago
Mapping Array Communication onto FIFO Communication - Towards an Implementation
In high-throughput real-time media processing systems, the communication between processing units is typically specified as multi-dimensional arrays. However, the implementation ...
Jeffrey Kang, Albert van der Werf, Paul E. R. Lipp...