Sciweavers

84 search results - page 11 / 17
» Designing and testing fault-tolerant techniques for SRAM-bas...
Sort
View
DAC
2011
ACM
12 years 7 months ago
Fault-tolerant 3D clock network
Clock tree synthesis is one of the most important and challenging problems in 3D ICs. The clock signals have to be delivered by through-silicon vias (TSVs) to different tiers with...
Chiao-Ling Lung, Yu-Shih Su, Shih-Hsiu Huang, Yiyu...
FTCS
1996
110views more  FTCS 1996»
13 years 8 months ago
Experimental Assessment of Parallel Systems
In the research reported in this paper, transient faults were injected in the nodes and in the communication subsystem (by using software fault injection) of a commercial parallel...
João Gabriel Silva, Joao Carreira, Henrique...
ISLPED
2009
ACM
132views Hardware» more  ISLPED 2009»
14 years 2 months ago
Enabling ultra low voltage system operation by tolerating on-chip cache failures
Extreme technology integration in the sub-micron regime comes with a rapid rise in heat dissipation and power density for modern processors. Dynamic voltage scaling is a widely us...
Amin Ansari, Shuguang Feng, Shantanu Gupta, Scott ...
ISLPED
2005
ACM
136views Hardware» more  ISLPED 2005»
14 years 1 months ago
Energy efficient SEU-tolerance in DVS-enabled real-time systems through information redundancy
Concerns about the reliability of real-time embedded systems that employ dynamic voltage scaling has recently been highlighted [1,2,3], focusing on transient-fault-tolerance techn...
Alireza Ejlali, Marcus T. Schmitz, Bashir M. Al-Ha...
STORAGESS
2006
ACM
14 years 1 months ago
Using device diversity to protect data against batch-correlated disk failures
Batch-correlated failures result from the manifestation of a common defect in most, if not all, disk drives belonging to the same production batch. They are much less frequent tha...
Jehan-François Pâris, Darrell D. E. L...