84 search results - page 4 / 17 » Designing and testing fault-tolerant techniques for SRAM-bas... |
CLEIEJ
2006
13 years 8 months ago
2006
The proposed software technique is a very low cost and an effective solution towards designing Byzantine fault tolerant computing application systems that are not so safety critic...
ICCAD
2008
IEEE
14 years 5 months ago
2008
IEEE
— Three-dimensional die stacking integration provides the ability to stack multiple layers of processed silicon with a large number of vertical interconnects. Through Silicon Via...
HASE
1997
IEEE
14 years 25 days ago
1997
IEEE
The Reusable Software Fault Tolerance Testbed ReSoFT was developed to facilitate the development and evaluation of high-assurance systems that require tolerance of both hardware...
ETS
2011
IEEE
12 years 8 months ago
2011
IEEE
Abstract—Networks-on-Chip (NoCs) are implicitly fault tolerant due to their inherent redundancy. They can overcome defective cores, links and switches. As a side effect, yield is...
FPGA
2000
ACM
14 years 6 days ago
2000
ACM
In recent years the application space of reconfigurable devices has grown to include many platforms with a strong need for fault tolerance. While these systems frequently contain ...