A low-overhead fault tolerance scheme for TSV-based 3D network on chip links

— Three-dimensional die stacking integration provides the ability to stack multiple layers of processed silicon with a large number of vertical interconnects. Through Silicon Vias (TSVs) provide a promising area- and power-efficient way to support communication between different stack layers. Unfortunately, low TSV yield significantly impacts design of three-dimensional die stacks with a large number of TSVs. This paper presents a defecttolerance technique for TSVs-based multi-bit links through an efficient and effective use of redundancy. This technique is ideally suited for three-dimensional network-on-chip (NoC) links. Simulation results demonstrate significant yield improvement, from 66% to 98%, with a low area cost (17% on a vertical link in a NoC switch, which leads a modest 2.1% increase the total switch area) in 130nm technology, with minimal impact of VLSI design and test flows.

• Type: Conference
• Year: 2008
• Where: ICCAD
• Authors: Igor Loi, Subhasish Mitra, Thomas H. Lee, Shinobu Fujita, Luca Benini
• Keywords: Hardware, ICCAD 2008, Low Tsv Yield, Three-dimensional Die Stacks, Total Switch Area