84 search results - page 9 / 17 » Designing and testing fault-tolerant techniques for SRAM-bas... |
FPGA
2010
ACM
14 years 3 months ago
2010
ACM
Triple Modular Redundancy (TMR) is a common reliability technique for mitigating single event upsets (SEUs) in FPGA designs operating in radiation environments. For FPGA systems t...
ISSTA
2009
ACM
14 years 3 months ago
2009
ACM
During testing, the execution of valid cases is only one part of the task. Checking the behavior in boundary situations and in the presence of errors is an equally important subje...
IOLTS
2008
IEEE
14 years 3 months ago
2008
IEEE
— Error correcting coding is the dominant technique to achieve acceptable soft-error rates in memory arrays. In many modern circuits, the number of memory elements in the random ...
ISCA
2007
IEEE
14 years 2 months ago
2007
IEEE
ACE analysis is a technique to provide an early reliability estimate for microprocessors. ACE analysis couples data from performance models with low level design details to identi...
DAC
2006
ACM
14 years 9 months ago
2006
ACM
The delay fault test pattern set generated by timing unaware commercial ATPG tools mostly affects very short paths, thereby increasing the escape chance of smaller delay defects. ...