Sleep transistors are effective to reduce dynamic and leakage power. The cluster-based design was proposed to reduce the sleep transistor area by clustering gates to minimize the ...
In this paper, we propose a fast and simple heuristic for the cosynthesis problem targeting the system-on-chip (SOC) design. The proposed algorithm covers from implementation sele...
Increasing our knowledge of how design affects behaviour in the workplace has a large potential for reducing electricity consumption. This would be beneficial for the environment ...
FinFET technology has been proposed as a promising alternative for deep sub-micro bulk CMOS technology, because of its better scalability. Previous work have studied the performan...
Feng Wang 0004, Yuan Xie, Kerry Bernstein, Yan Luo
- Data path connection elements, such as multiplexers, consume a significant amount of area on a VLSI chip, especially for FPGA designs. Multiplexer optimization is a difficult pro...