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» Designing floating codes for expected performance
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139
Voted
RSP
2000
IEEE
111views Control Systems» more  RSP 2000»
15 years 7 months ago
Reconfigurable Instruction Set Processors: A Survey
Reconfigurable instruction set processors have the capability to adapt their instruction sets to the application being executed through a reconfiguration in their hardware. Throug...
Francisco Barat, Rudy Lauwereins
135
Voted
CODES
2010
IEEE
15 years 25 days ago
Dynamic, non-linear cache architecture for power-sensitive mobile processors
Today, mobile smartphones are expected to be able to run the same complex, algorithm-heavy, memory-intensive applications that were originally designed and coded for generalpurpos...
Garo Bournoutian, Alex Orailoglu
145
Voted
MM
2010
ACM
251views Multimedia» more  MM 2010»
15 years 3 months ago
A cognitive approach for effective coding and transmission of 3D video
Reliable delivery of 3D video contents to a wide set of users is expected to be the next big revolution in multimedia applications provided that it is possible to grant a certain ...
Simone Milani, Giancarlo Calvagno
104
Voted
CODES
2009
IEEE
15 years 9 months ago
A variation-tolerant scheduler for better than worst-case behavioral synthesis
– There has been a recent shift in design paradigms, with many turning towards yield-driven approaches to synthesize and design systems. A major cause of this shift is the contin...
Jason Cong, Albert Liu, Bin Liu
129
Voted
DAC
2002
ACM
16 years 3 months ago
An integer linear programming based approach for parallelizing applications in On-chip multiprocessors
With energy consumption becoming one of the first-class optimization parameters in computer system design, compilation techniques that consider performance and energy simultaneous...
Ismail Kadayif, Mahmut T. Kandemir, Ugur Sezer