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» Designing for Xilinx XC6200 FPGAs
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GLVLSI
2003
IEEE
130views VLSI» more  GLVLSI 2003»
14 years 27 days ago
Zero overhead watermarking technique for FPGA designs
FPGAs, because of their re-programmability, are becoming very popular for creating and exchanging VLSI intellectual properties (IPs) in the reuse-based design paradigm. Existing w...
Adarsh K. Jain, Lin Yuan, Pushkin R. Pari, Gang Qu
FPGA
2003
ACM
138views FPGA» more  FPGA 2003»
14 years 25 days ago
Automatic transistor and physical design of FPGA tiles from an architectural specification
One of the most difficult and time-consuming steps in the creation of an FPGA is its transistor-level design and physical layout. Modern commercial FPGAs typically consume anywher...
Ketan Padalia, Ryan Fung, Mark Bourgeault, Aaron E...
ICCAD
1995
IEEE
106views Hardware» more  ICCAD 1995»
13 years 11 months ago
Re-engineering of timing constrained placements for regular architectures
In a typical design ow, the design may be altered slightly several times after the initial design cycle according to minor changes in the design speci cation either as a result o...
Anmol Mathur, K. C. Chen, C. L. Liu
CHES
2009
Springer
171views Cryptology» more  CHES 2009»
14 years 8 months ago
Trojan Side-Channels: Lightweight Hardware Trojans through Side-Channel Engineering
Abstract. The general trend in semiconductor industry to separate design from fabrication leads to potential threats from untrusted integrated circuit foundries. In particular, mal...
Christof Paar, Lang Lin, Markus Kasper, Tim Gü...
FPGA
2010
ACM
243views FPGA» more  FPGA 2010»
14 years 4 months ago
Bit-level optimization for high-level synthesis and FPGA-based acceleration
d hardware design from behavior-level abstraction has drawn wide interest in FPGA-based acceleration and configurable computing research field. However, for many high-level progra...
Jiyu Zhang, Zhiru Zhang, Sheng Zhou, Mingxing Tan,...