114 search results - page 3 / 23 » Designing for Xilinx XC6200 FPGAs |
DATE
2002
IEEE
14 years 17 days ago
2002
IEEE
We present an area and delay estimator in the context of a compiler that takes in high level signal and image processing applications described in MATLAB and performs automatic de...
ISCIS
2009
Springer
14 years 2 months ago
2009
Springer
This paper presents hardware design of a family of soft cores that improve image quality on low cost digital displaying devices with limited color palette. The twoelement half-toni...
DATE
2002
IEEE
14 years 17 days ago
2002
IEEE
In this paper, we present an efficient methodology to validate high performance algorithms and prototype them using reconfigurable hardware. We follow a strict topdown Hardware/So...
ERSA
2010
13 years 5 months ago
2010
Partial reconfiguration (PR) enhances traditional FPGA-based high-performance reconfigurable computing by providing additional benefits such as reduced area and memory requirements...
FPGA
2004
ACM
14 years 1 months ago
2004
ACM
FPGAs normally operate at whatever clock rate is appropriate for the loaded configuration. When FPGAs are used as computational devices in a larger system, however, it is better ...