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106
Voted
ISCAS
2003
IEEE
89views Hardware» more  ISCAS 2003»
15 years 9 months ago
Synthesizing checkers for on-line verification of System-on-Chip designs
In modern System-on-Chip (SoC) designs verification becomes the major bottleneck. Since by using state-of-theart techniques complete designs cannot be fully formally verified, it ...
Rolf Drechsler
87
Voted
DATE
2006
IEEE
151views Hardware» more  DATE 2006»
15 years 9 months ago
An 830mW, 586kbps 1024-bit RSA chip design
This paper presents an RSA hardware design that simultaneously achieves high-performance and lowpower. A bit-oriented, split modular multiplication algorithm and architecture are ...
Chingwei Yeh, En-Feng Hsu, Kai-Wen Cheng, Jinn-Shy...
118
Voted
ISCAS
2005
IEEE
158views Hardware» more  ISCAS 2005»
15 years 9 months ago
Designing optimized pipelined global interconnects: algorithms and methodology impact
— As across-chip wire delays exceed a clock cycle, interconnect pipelining becomes essential. However, the arbitrary insertion of flip-flops can change the differentials of lat...
Vidyasagar Nookala, Sachin S. Sapatnekar
141
Voted
ACSAC
2003
IEEE
15 years 9 months ago
Security Design in Online Games
The emergence of online games has fundamentally changed security requirements for computer games, which previously were largely concerned with copy protection. In this paper, we e...
Jeff Jianxin Yan
ICMAS
2000
15 years 5 months ago
Architecture-Centric Object-Oriented Design Method for Multi-Agent Systems
s This paper introduces an architecture-centric object-oriented design method for MAS (Multi-Agent Systems) using the extended UML (Unified Modeling Language). The UML extension is...
Hongsoon Yim, Kyehyun Cho, Sung Joo Park, Jongwoo ...