453 search results - page 54 / 91 » Designing hardware with dynamic memory abstraction |
113
Voted
IEEEPACT
2006
IEEE
15 years 9 months ago
2006
IEEE
Modern out-of-order processors with non-blocking caches exploit Memory-Level Parallelism (MLP) by overlapping cache misses in a wide instruction window. The exploitation of MLP, h...
151
Voted
CASES
2008
ACM
15 years 5 months ago
2008
ACM
Java applications rely on Just-In-Time (JIT) compilers or adaptive compilers to generate and optimize binary code at runtime to boost performance. In conventional Java Virtual Mac...
137
Voted
DATE
2003
IEEE
15 years 9 months ago
2003
IEEE
Novel reconfigurable computing architectures exploit the inherent parallelism available in many signalprocessing problems. These architectures often consist of networks of compute...
144
Voted
ASPLOS
2012
ACM
13 years 11 months ago
2012
ACM
The rise of multi-core processors has shifted performance efforts towards parallel programs. However, single-threaded code, whether from legacy programs or ones difficult to para...
105
Voted
ISCA
2008
IEEE
15 years 10 months ago
2008
IEEE
Modern processors rely on memory dependence prediction to execute load instructions as early as possible, speculating that they are not dependent on an earlier, unissued store. To...