Sciweavers

31 search results - page 1 / 7
» Designing packet buffers for router linecards
Sort
View
TON
2008
124views more  TON 2008»
13 years 10 months ago
Designing packet buffers for router linecards
-- Internet routers and Ethernet switches contain packet buffers to hold packets during times of congestion. Packet buffers are at the heart of every packet switch and router, whic...
Sundar Iyer, Ramana Rao Kompella, Nick McKeown
ANCS
2005
ACM
14 years 4 months ago
Gigabit routing on a software-exposed tiled-microprocessor
This paper investigates the suitability of emerging tiled-architectures, equipped with low-latency on-chip networks, for high-performance network routing. In this paper, we presen...
Umar Saif, James W. Anderson, Anthony Degangi, Ana...
DSD
2009
IEEE
118views Hardware» more  DSD 2009»
14 years 5 months ago
Internet-Router Buffered Crossbars Based on Networks on Chip
—The scalability and performance of the Internet depends critically on the performance of its packet switches. Current packet switches are based on single-hop crossbar fabrics, w...
Kees Goossens, Lotfi Mhamdi, Iria Varela Senin
SIGCOMM
2004
ACM
14 years 4 months ago
Sizing router buffers
All Internet routers contain buffers to hold packets during times of congestion. Today, the size of the buffers is determined by the dynamics of TCP’s congestion control algor...
Guido Appenzeller, Isaac Keslassy, Nick McKeown
NOCS
2010
IEEE
13 years 8 months ago
Design of a High-Throughput Distributed Shared-Buffer NoC Router
Router microarchitecture plays a central role in the performance of an on-chip network (NoC). Buffers are needed in routers to house incoming flits which cannot be immediately forw...
Rohit Sunkam Ramanujam, Vassos Soteriou, Bill Lin,...