1226 search results - page 17 / 246 » Designing systems-on-chip using cores |
FPL
2006
Springer
13 years 11 months ago
2006
Springer
In this paper we introduce a new method to identify IP cores in an FPGA by analyzing the content of lookup tables. This techniques can be used to identify registered cores for IP ...
ISCAS
2003
IEEE
14 years 1 months ago
2003
IEEE
the interconnection among the IP cores with all description levels This paper presents an automatic interconnection rectification (AIR)technique to correct the misplaced interconne...
DSD
2003
IEEE
14 years 1 months ago
2003
IEEE
This paper proposes a methodology and a basic structure for the design of wrappers used to adapt cores for use as bus masters. The AMBA AHB protocol is used as a case study in thi...
MSE
2003
IEEE
14 years 1 months ago
2003
IEEE
The increasing gap between design productivity and chip complexity, and emerging systems-on-a-chip (SoC) have led to the wide utilization of reusable intellectual property (IP) co...
DAC
2004
ACM
14 years 1 months ago
2004
ACM
The Pentium® 4 processor architecture uses a 2x frequency core clock[1] to implement low latency integer ops. Low Voltage Swing logic circuits implemented in 90nm technology[2] m...