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VTS
2000
IEEE
167views Hardware» more  VTS 2000»
13 years 12 months ago
Path Selection for Delay Testing of Deep Sub-Micron Devices Using Statistical Performance Sensitivity Analysis
The performance of deep sub-micron designs can be affected by various parametric variations, manufacturing defects, noise or even modeling errors that are all statistical in natur...
Jing-Jia Liou, Kwang-Ting Cheng, Deb Aditya Mukher...
ISICT
2003
13 years 9 months ago
On the automated implementation of modal logics used to verify security protocols
: Formal verification provides a rigid and thorough means of evaluating the correctness of cryptographic protocols so that even subtle defects can be identified. As the application...
Tom Coffey, Reiner Dojen, Tomas Flanagan
DAC
2005
ACM
14 years 8 months ago
Designing logic circuits for probabilistic computation in the presence of noise
As Si CMOS devices are scaled down into the nanoscale regime, current computer architecture approaches are reaching their practical limits. Future nano-architectures will confront...
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, Will...
MTDT
2000
IEEE
137views Hardware» more  MTDT 2000»
13 years 12 months ago
Diagnostic Testing of Embedded Memories Based on Output Tracing
A new approach to diagnostic testing of embedded memories is presented which enables the design of tests that provide complete detection and distinguishing of all faults in a give...
Dirk Niggemeyer, Elizabeth M. Rudnick, Michael Red...
NA
2010
85views more  NA 2010»
13 years 6 months ago
The reliability/cost trade-off for a class of ODE solvers
In the numerical solution of ODEs, it is now possible to develop efficient techniques that will deliver approximate solutions that are piecewise polynomials. The resulting methods...
Wayne H. Enright, Li Yan