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ISCAS
2007
IEEE
133views Hardware» more  ISCAS 2007»
14 years 2 months ago
Design of a Massively Parallel Vision Processor based on Multi-SIMD Architecture
— Increasing demands for robust image recognition systems require vision processors not only with enormous computational capacities but also with sufficient flexibility to hand...
Kota Yamaguchi, Yoshihiro Watanabe, Takashi Komuro...
HPCC
2005
Springer
14 years 1 months ago
Trace-Based Parallel Performance Overhead Compensation
Abstract. Tracing parallel programs to observe their performance introduces intrusion as the result of trace measurement overhead. If post-mortem trace analysis does not compensate...
Felix Wolf, Allen D. Malony, Sameer Shende, Alan M...
OOPSLA
2005
Springer
14 years 1 months ago
Lifting sequential graph algorithms for distributed-memory parallel computation
This paper describes the process used to extend the Boost Graph Library (BGL) for parallel operation with distributed memory. The BGL consists of a rich set of generic graph algor...
Douglas Gregor, Andrew Lumsdaine
CISIS
2010
IEEE
14 years 1 months ago
A Parallel Programming Framework for Multi-core DNA Sequence Alignment
—A new parallel programming framework for DNA sequence alignment in homogeneous multi-core processor architectures is proposed. Contrasting with traditional coarse-grained parall...
Tiago Jose Barreiros Martins de Almeida, Nuno Fili...
ARITH
2003
IEEE
14 years 1 months ago
A New Iterative Structure for Hardware Division: The Parallel Paths Algorithm
This paper presents a new approach to hardware division—the parallel paths algorithm. In this approach, prescaling allows the division recurrence to be implemented by three proc...
Eric Rice, Richard Hughey