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» Diagnosis of Delay Defects Using Statistical Timing Models
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EURODAC
1994
IEEE
209views VHDL» more  EURODAC 1994»
13 years 11 months ago
MOS VLSI circuit simulation by hardware accelerator using semi-natural models
- The accelerator is destined to circuit-level simulation of digital and analog/digital MOS VLSI'c containing of up to 100 thousand transistors (with 16 Mb RAM host-machine). ...
Victor V. Denisenko
ASPDAC
2004
ACM
102views Hardware» more  ASPDAC 2004»
14 years 23 days ago
TranGen: a SAT-based ATPG for path-oriented transition faults
— This paper presents a SAT-based ATPG tool targeting on a path-oriented transition fault model. Under this fault model, a transition fault is detected through the longest sensit...
Kai Yang, Kwang-Ting Cheng, Li-C. Wang
DATAMINE
2006
164views more  DATAMINE 2006»
13 years 7 months ago
Fast Distributed Outlier Detection in Mixed-Attribute Data Sets
Efficiently detecting outliers or anomalies is an important problem in many areas of science, medicine and information technology. Applications range from data cleaning to clinica...
Matthew Eric Otey, Amol Ghoting, Srinivasan Partha...
ICCAD
2003
IEEE
140views Hardware» more  ICCAD 2003»
14 years 4 months ago
Block-based Static Timing Analysis with Uncertainty
Static timing analysis is a critical step in design of any digital integrated circuit. Technology and design trends have led to significant increase in environmental and process v...
Anirudh Devgan, Chandramouli V. Kashyap
NIPS
2008
13 years 8 months ago
Accelerating Bayesian Inference over Nonlinear Differential Equations with Gaussian Processes
Identification and comparison of nonlinear dynamical system models using noisy and sparse experimental data is a vital task in many fields, however current methods are computation...
Ben Calderhead, Mark Girolami, Neil D. Lawrence