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» Diagonal Circuit Identity Testing and Lower Bounds
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DAC
2009
ACM
14 years 8 months ago
Computing bounds for fault tolerance using formal techniques
Continuously shrinking feature sizes result in an increasing susceptibility of circuits to transient faults, e.g. due to environmental radiation. Approaches to implement fault tol...
André Sülflow, Görschwin Fey, Rol...
ASPDAC
1998
ACM
119views Hardware» more  ASPDAC 1998»
13 years 12 months ago
Integer Programming Models for Optimization Problems in Test Generation
— Test Pattern Generation for combinational circuits entails the identification of primary input assignments for detecting each fault in a set of target faults. An extension to ...
João P. Marques Silva
ICCD
2003
IEEE
109views Hardware» more  ICCD 2003»
14 years 4 months ago
Independent Test Sequence Compaction through Integer Programming
We discuss the compaction of independent test sequences for sequential circuits. Our first contribution is the formulation of this problem as an integer program, which we then so...
Petros Drineas, Yiorgos Makris
STACS
2000
Springer
13 years 11 months ago
The Complexity of Planarity Testing
We clarify the computational complexity of planarity testing, by showing that planarity testing is hard for L, and lies in SL. This nearly settles the question, since it is widely...
Eric Allender, Meena Mahajan
JCSS
2000
116views more  JCSS 2000»
13 years 7 months ago
Time-Space Tradeoffs for Satisfiability
We give the first nontrivial model-independent time-space tradeoffs for satisfiability. Namely, we show that SAT cannot be solved simultaneously in n1+o(1) time and n1space for an...
Lance Fortnow