Sciweavers

410 search results - page 14 / 82
» Diagonal routing in high performance microprocessor design
Sort
View
NOCS
2007
IEEE
14 years 2 months ago
Implementation and Evaluation of a Dynamically Routed Processor Operand Network
— Microarchitecturally integrated on-chip networks, or micronets, are candidates to replace busses for processor component interconnect in future processor designs. For micronets...
Paul Gratz, Karthikeyan Sankaralingam, Heather Han...
VTC
2008
IEEE
165views Communications» more  VTC 2008»
14 years 2 months ago
Operation and Performance of Vehicular Ad-Hoc Routing Protocols in Realistic Environments
—Vehicle-to-vehicle and vehicle-to-infrastructure wireless communications are currently under development to improve traffic efficiency and safety. Routing protocols enabling mul...
Ramon Bauza, Javier Gozálvez, Miguel Sepulc...
ICCAD
2007
IEEE
64views Hardware» more  ICCAD 2007»
14 years 5 months ago
A simultaneous bus orientation and bused pin flipping algorithm
— The orientation of a bus is defined as the direction from the Least Significant Bit (LSB) to the Most Significant Bit (MSB). Bused pin flipping is a property that allows severa...
Fan Mo, Robert K. Brayton
ICCD
2007
IEEE
106views Hardware» more  ICCD 2007»
14 years 9 days ago
Transparent mode flip-flops for collapsible pipelines
Prior work has shown that collapsible pipelining techniques have the potential to significantly reduce clocking activity, which can consume up to 70% of the dynamic power in moder...
Eric L. Hill, Mikko H. Lipasti
ISCAS
2006
IEEE
104views Hardware» more  ISCAS 2006»
14 years 2 months ago
Average lengths of wire routing under M-architecture and X-architecture
— The X-architecture is a new integrated-circuit wiring technique in the physical design. Compared with the currently used M-architecture, which uses either horizontal or vertica...
S. P. Shang, Xiaodong Hu, Tong Jing