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» Diagonal routing in high performance microprocessor design
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FCCM
2007
IEEE
165views VLSI» more  FCCM 2007»
13 years 10 months ago
Sparse Matrix-Vector Multiplication Design on FPGAs
Creating a high throughput sparse matrix vector multiplication (SpMxV) implementation depends on a balanced system design. In this paper, we introduce the innovative SpMxV Solver ...
Junqing Sun, Gregory D. Peterson, Olaf O. Storaasl...
MOBIHOC
2008
ACM
14 years 8 months ago
Routing performance analysis of human-driven delay tolerant networks using the truncated levy walk model
The routing performance of delay tolerant networks (DTN) is highly correlated with the distribution of inter-contact times (ICT), the time period between two successive contacts o...
Seongik Hong, Injong Rhee, Seong Joon Kim, Kyungha...
MOBIHOC
2005
ACM
14 years 8 months ago
Efficient geographic routing in multihop wireless networks
We propose a new link metric called normalized advance (NADV) for geographic routing in multihop wireless networks. NADV selects neighbors with the optimal trade-off between proxi...
Seungjoon Lee, Bobby Bhattacharjee, Suman Banerjee
FPGA
2005
ACM
137views FPGA» more  FPGA 2005»
14 years 2 months ago
HARP: hard-wired routing pattern FPGAs
Modern FPGA architectures provide ample routing resources so that designs can be routed successfully. The routing architecture is designed to handle versatile connection configur...
Satish Sivaswamy, Gang Wang, Cristinel Ababei, Kia...
ICS
2004
Tsinghua U.
14 years 1 months ago
Cluster prefetch: tolerating on-chip wire delays in clustered microarchitectures
The growing dominance of wire delays at future technology points renders a microprocessor communication-bound. Clustered microarchitectures allow most dependence chains to execute...
Rajeev Balasubramonian