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» Diagonal routing in high performance microprocessor design
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DATE
2002
IEEE
124views Hardware» more  DATE 2002»
14 years 1 months ago
Crosstalk Alleviation for Dynamic PLAs
—The dynamic programmable logic array (PLA) style has become popular in designing high-performance microprocessors because of its high speed and predictable routing delay. Howeve...
Tzyy-Kuen Tien, Tong-Kai Tsai, Shih-Chieh Chang
ICWN
2004
13 years 9 months ago
Sustaining Performance Under Traffic Overload
In this paper, we investigate the performance of wireless ad hoc networks with traffic loads beyond saturation. While it is desirable to operate a network below saturation, an ad h...
Saman Desilva, Rajendra V. Boppana
ISCAS
2007
IEEE
128views Hardware» more  ISCAS 2007»
14 years 2 months ago
Collaborative Routing Architecture for FPGA
— In this paper we present the Collaborative Routing Architecture (CRA), a routing architecture specially designed to achieve high efficiency in hardware and competitive delay p...
Yaling Ma, Mingjie Lin
ISCA
1997
IEEE
108views Hardware» more  ISCA 1997»
14 years 20 days ago
The SGI Origin: A ccNUMA Highly Scalable Server
The SGI Origin 2000 is a cache-coherent non-uniform memory access (ccNUMA) multiprocessor designed and manufactured by Silicon Graphics, Inc. The Origin system was designed from t...
James Laudon, Daniel Lenoski
IEEEPACT
2002
IEEE
14 years 1 months ago
Efficient Interconnects for Clustered Microarchitectures
Clustering is an effective microarchitectural technique for reducing the impact of wire delays, the complexity, and the power requirements of microprocessors. In this work, we inv...
Joan-Manuel Parcerisa, Julio Sahuquillo, Antonio G...