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» Diagonal routing in high performance microprocessor design
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DATE
2009
IEEE
83views Hardware» more  DATE 2009»
14 years 3 months ago
Performance-driven dual-rail insertion for chip-level pre-fabricated design
In recent years, pre-fabricated design styles grow up rapidly to amortize the mask cost. However, the interconnection delay of the pre-fabricated design styles slows down the circ...
Fu-Wei Chen, Yi-Yu Liu
ASPDAC
2005
ACM
115views Hardware» more  ASPDAC 2005»
14 years 2 months ago
Low-power domino circuits using NMOS pull-up on off-critical paths
- Domino logic is used extensively in high speed microprocessor datapath design. Although domino gates have small propagation delay, they consume relatively more power. We propose ...
Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhij...
DAC
2003
ACM
14 years 1 months ago
Low-power design methodology for an on-chip bus with adaptive bandwidth capability
This paper describes a low-power design methodology for a bus architecture based on hybrid current/voltage mode signaling for deep sub-micrometer on-chip interconnects that achiev...
Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III
CORR
2006
Springer
71views Education» more  CORR 2006»
13 years 8 months ago
Wreath Products in Stream Cipher Design
The paper develops a novel approach to stream cipher design: Both the state update function and the output function of the corresponding pseudorandom generators are compositions of...
Vladimir Anashin
PCRCW
1997
Springer
14 years 19 days ago
ChaosLAN: Design and Implementation of a Gigabit LAN Using Chaotic Routing
In recent years, theChaos Project at theUniversityofWashingtonhas analyzed and simulated a dozen routing algorithms. Three new routing algorithms have been invented; of these, the...
Neil R. McKenzie, Kevin Bolding, Carl Ebeling, Law...