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» Diagonal routing in high performance microprocessor design
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ICCCN
2007
IEEE
14 years 10 days ago
Load-aware Traffic Engineering for Mesh Networks
Abstract--The static nature of mesh nodes imposes requirements for designing routing metrics that support high throughput and low packet delay. This paper considers the problem of ...
Devu Manikantan Shila, Tricha Anjali
IJNSEC
2007
82views more  IJNSEC 2007»
13 years 8 months ago
On Software Implementation of Fast DDP-based Ciphers
Data-dependent (DD) permutations (DDP) are discussed as a cryptographic primitive for the design of fast hardware, firmware, and software encryption systems. DDP can be performed...
Nikolay A. Moldovyan, Peter A. Moldovyanu, Douglas...
DAC
2003
ACM
14 years 9 months ago
Dynamic hardware/software partitioning: a first approach
Partitioning an application among software running on a microprocessor and hardware co-processors in on-chip configurable logic has been shown to improve performance and energy co...
Greg Stitt, Roman L. Lysecky, Frank Vahid
ICPADS
2005
IEEE
14 years 2 months ago
Efficient Distributed QoS Routing Protocol for MPLS Networks
- This paper proposes a new distributed QoS routing protocol, called Efficient Distributed QoS Routing (EDQR), for MPLS networks. The path searching algorithm of EDQR considers an ...
Man-Ching Yuen, Weijia Jia, Chi-Chung Cheung
MICRO
2006
IEEE
144views Hardware» more  MICRO 2006»
14 years 2 months ago
Die Stacking (3D) Microarchitecture
3D die stacking is an exciting new technology that increases transistor density by vertically integrating two or more die with a dense, high-speed interface. The result of 3D die ...
Bryan Black, Murali Annavaram, Ned Brekelbaum, Joh...