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» Diagonal routing in high performance microprocessor design
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SASN
2006
ACM
14 years 1 months ago
Attack-resilient hierarchical data aggregation in sensor networks
In a large sensor network, in-network data aggregation, i.e., combining partial results at intermediate nodes during message routing, significantly reduces the amount of communic...
Sankardas Roy, Sanjeev Setia, Sushil Jajodia
MOBISYS
2009
ACM
14 years 8 months ago
Predictive methods for improved vehicular WiFi access
With the proliferation of WiFi technology, many WiFi networks are accessible from vehicles on the road making vehicular WiFi access realistic. However, several challenges exist: l...
Pralhad Deshpande, Anand Kashyap, Chul Sung, Samir...
FPGA
2003
ACM
167views FPGA» more  FPGA 2003»
14 years 17 days ago
A scalable 2 V, 20 GHz FPGA using SiGe HBT BiCMOS technology
This paper presents a new power saving, high speed FPGA design enhancing a previous SiGe CML FPGA based on the Xilinx 6200 FPGA. The design aims at having a higher performance but...
Jong-Ru Guo, Chao You, Kuan Zhou, Bryan S. Goda, R...
SIGCOMM
2003
ACM
14 years 18 days ago
A measurement-based analysis of multihoming
Multihoming has traditionally been employed by stub networks to enhance the reliability of their network connectivity. With the advent of commercial “intelligent route control...
Aditya Akella, Bruce M. Maggs, Srinivasan Seshan, ...
MICRO
2009
IEEE
99views Hardware» more  MICRO 2009»
14 years 2 months ago
Low-cost router microarchitecture for on-chip networks
On-chip networks are critical to the scaling of future multicore processors. The challenge for on-chip network is to reduce the cost including power consumption and area while pro...
John Kim