35 search results - page 2 / 7 » Die Stacking (3D) Microarchitecture |
ISCA
2007
IEEE
14 years 1 months ago
2007
IEEE
Much like multi-storey buildings in densely packed metropolises, three-dimensional (3D) chip structures are envisioned as a viable solution to skyrocketing transistor densities an...
ETS
2010
IEEE
13 years 8 months ago
2010
IEEE
Testing of 3D stacked ICs (SICs) is becoming increasingly important in the semiconductor industry. In this paper, we address the problem of test architecture optimization for 3D s...
ICCD
2004
IEEE
14 years 4 months ago
2004
IEEE
This short paper explores an implementation of a new technology called 3D die stacking and describes research activity at Intel. 3D die stacking is the bonding of two die either f...
ICCAD
2008
IEEE
14 years 4 months ago
2008
IEEE
— Three-dimensional die stacking integration provides the ability to stack multiple layers of processed silicon with a large number of vertical interconnects. Through Silicon Via...
TCAD
2011
13 years 2 months ago
2011
—Pre-bond testing of 3-D stacked integrated circuits (ICs) involves testing each individual die before bonding. The overall yield of 3-D ICs improves with pre-bond testability be...