35 search results - page 4 / 7 » Die Stacking (3D) Microarchitecture |
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
Abstract—Convergence of communication, consumer applications and computing within mobile systems pushes memory requirements both in terms of size, bandwidth and power consumption...
SLIP
2009
ACM
14 years 1 months ago
2009
ACM
Individual dies in 3D integrated circuits are connected using throughsilicon-vias (TSVs). TSVs not only increase manufacturing cost, but also incur silicon area, delay, and power ...
3DIC
2009
IEEE
14 years 2 months ago
2009
IEEE
The first memristor, originally theorized by Dr. Leon Chua in 1971, was identified by a team at HP Labs in 2008. This new fundamental circuit element is unique in that its resis...
ISCAS
2005
IEEE
14 years 1 months ago
2005
IEEE
— We designed a 3D integrated multi-chip module that uses non-galvanic capacitive coupling to provide bi-directional communication and exchange power supply between two separate ...
CASES
2010
ACM
13 years 4 months ago
2010
ACM
3-D circuit-level integration is a chip fabrication technique in which two or more dies are stacked and combined into a single circuit through the use of vertical electroconductiv...