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MICRO
2003
IEEE
109views Hardware» more  MICRO 2003»
14 years 27 days ago
TLC: Transmission Line Caches
It is widely accepted that the disproportionate scaling of transistor and conventional on-chip interconnect performance presents a major barrier to future high performance systems...
Bradford M. Beckmann, David A. Wood
JCDL
2010
ACM
199views Education» more  JCDL 2010»
14 years 21 days ago
Crowdsourcing the assembly of concept hierarchies
The“wisdom of crowds”is accomplishing tasks that are cumbersome for individuals yet cannot be fully automated by means of specialized computer algorithms. One such task is the...
Kai Eckert, Mathias Niepert, Christof Niemann, Cam...
PLDI
2010
ACM
14 years 21 days ago
Adversarial memory for detecting destructive races
Multithreaded programs are notoriously prone to race conditions, a problem exacerbated by the widespread adoption of multi-core processors with complex memory models and cache coh...
Cormac Flanagan, Stephen N. Freund
PLDI
2010
ACM
14 years 21 days ago
Finding low-utility data structures
Many opportunities for easy, big-win, program optimizations are missed by compilers. This is especially true in highly layered Java applications. Often at the heart of these misse...
Guoqing Xu, Nick Mitchell, Matthew Arnold, Atanas ...
ISCA
2000
IEEE
99views Hardware» more  ISCA 2000»
14 years 11 hour ago
Transient fault detection via simultaneous multithreading
Smaller feature sizes, reduced voltage levels, higher transistor counts, and reduced noise margins make future generations of microprocessors increasingly prone to transient hardw...
Steven K. Reinhardt, Shubhendu S. Mukherjee