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DFT
2007
IEEE
109views VLSI» more  DFT 2007»
14 years 2 months ago
Safety Evaluation of NanoFabrics
Chemically Assembled Electronic Nanotechnology is a promising alternative to CMOS fabrication. In particular, the nanoFabric has proven to be a viable solution for implementing di...
Michelangelo Grosso, Maurizio Rebaudengo, Matteo S...
ISCAS
2007
IEEE
148views Hardware» more  ISCAS 2007»
14 years 2 months ago
Bandwidth Mismatch Correction for a Two-Channel Time-Interleaved A/D Converter
— Mismatches between sample-and-hold (S/H) circuits in a time-interleaved analog-to-digital data converter (ADC) cause undesirable distortions in the output spectrum. To reduce t...
Patrick Satarzadeh, Bernard C. Levy, Paul J. Hurst
ETS
2006
IEEE
106views Hardware» more  ETS 2006»
14 years 1 months ago
"Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC
In this paper, complex mixed signal circuits such as SiP or SOC including several ADCs and DACs are considered. A new DFT technique is proposed allowing the test of this complete ...
Vincent Kerzerho, Philippe Cauvet, Serge Bernard, ...
ISCAS
2005
IEEE
275views Hardware» more  ISCAS 2005»
14 years 1 months ago
A low dropout, CMOS regulator with high PSR over wideband frequencies
Modern System-on-Chip (SoC) environments are swamped in high frequency noise that is generated by RF and digital circuits and propagated onto supply rails through capacitive coupli...
Vishal Gupta, Gabriel A. Rincón-Mora
ICDAR
2003
IEEE
14 years 29 days ago
An Evolutionary Algorithm for General Symbol Segmentation
A new system is presented for general symbol segmentation, which is applicable for segmentation of any connected string of symbols, including characters and line diagrams. Using a...
Stephen Pearce, Maher Ahmed