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ISQED
2003
IEEE
113views Hardware» more  ISQED 2003»
14 years 28 days ago
Using Integer Equations for High Level Formal Verification Property Checking
This paper describes the use of integer equations for high level modeling digital circuits for application of formal verification properties at this level. Most formal verificatio...
Bijan Alizadeh, Mohammad Reza Kakoee
ISQED
2003
IEEE
109views Hardware» more  ISQED 2003»
14 years 28 days ago
Modeling and Analysis of Power Distribution Networks for Gigabit Applications
—As the operating frequency of digital systems increases and voltage swing decreases, it becomes very important to characterize and analyze power distribution networks (PDNs) acc...
Wendemagegnehu T. Beyene, Chuck Yuan, Joong-Ho Kim...
ITC
2002
IEEE
72views Hardware» more  ITC 2002»
14 years 17 days ago
Test Point Insertion that Facilitates ATPG in Reducing Test Time and Data Volume
Efficient production testing is frequently hampered because current digital circuits require test sets which are too large. These test sets can be reduced significantly by means...
M. J. Geuzebroek, J. Th. van der Linden, A. J. van...
EH
2000
IEEE
109views Hardware» more  EH 2000»
14 years 2 days ago
Bidirectional Incremental Evolution in Extrinsic Evolvable Hardware
Evolvable Hardware (EHW) has been proposed as a new technique to design complex systems. Often, complex systems turn out to be very difficult to evolve. The problem is that a gen...
Tatiana Kalganova
ICCAD
1998
IEEE
105views Hardware» more  ICCAD 1998»
13 years 12 months ago
Fanout optimization under a submicron transistor-level delay model
In this paper we present a new fanout optimization algorithm which is particularly suitable for digital circuits designed with submicron CMOS technologies. Restricting the class o...
Pasquale Cocchini, Massoud Pedram, Gianluca Piccin...