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ASPDAC
2005
ACM
104views Hardware» more  ASPDAC 2005»
13 years 9 months ago
Skew scheduling and clock routing for improved tolerance to process variations
The synthesis of clock network in the presence of process variation is becoming a vital design issue towards the performance of digital circuits. In this paper, we propose a clock ...
Ganesh Venkataraman, Cliff C. N. Sze, Jiang Hu
ASPDAC
2005
ACM
99views Hardware» more  ASPDAC 2005»
13 years 9 months ago
Implication of assertion graphs in GSTE
- We address the problem of implication of assertion graphs that occur in generalized symbolic trajectory evaluation (GSTE). GSTE has demonstrated its powerful capacity in formal v...
Guowu Yang, Jin Yang, William N. N. Hung, Xiaoyu S...
DAC
2008
ACM
13 years 9 months ago
Analog parallelism in ring-based VCOs
The performance advantages in parallel ring-based VCOs are explored. When the number of VCOs is doubled, the parallel VCOs enhance phase noise by 3dB, and the within-chip process-...
Daeik D. Kim, Choongyeun Cho, Jonghae Kim
FPL
2008
Springer
154views Hardware» more  FPL 2008»
13 years 9 months ago
Numerical function generators using bilinear interpolation
Two-variable numerical functions are widely used in various applications, such as computer graphics and digital signal processing. Fast and compact hardware implementations are re...
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
IJCAI
2007
13 years 9 months ago
Modeling When Connections Are the Problem
Most AI diagnostic reasoning approaches model components and but not their interconnections, and when they do model interconnections, they model the possibility that a connection ...
Johan de Kleer