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FPGA
2009
ACM
482views FPGA» more  FPGA 2009»
14 years 7 days ago
A 17ps time-to-digital converter implemented in 65nm FPGA technology
This paper presents a new architecture for time-to-digital conversion enabling a time resolution of 17ps over a range of 50ns with a conversion rate of 20MS/s. The proposed archit...
Claudio Favi, Edoardo Charbon
IFIP
2001
Springer
14 years 2 days ago
Random Adjacent Sequences: An Efficient Solution for Logic BIST
: High defect coverage requires good coverage of different fault types. In this paper, we present a comprehensive test vector generation technique for BIST, called Random Single In...
René David, Patrick Girard, Christian Landr...
ISQED
2010
IEEE
128views Hardware» more  ISQED 2010»
13 years 9 months ago
A novel all-digital fractional-N frequency synthesizer architecture with fast acquisition and low spur
Digital implementation of analog function is becoming attractive in CMOS ICs, given the low supply voltage of ultra-scaled process. The conventional fractional-N frequency synthes...
Jun Zhao, Yong-Bin Kim
NIPS
2001
13 years 9 months ago
Orientation-Selective aVLSI Spiking Neurons
We describe a programmable multi-chip VLSI neuronal system that can be used for exploring spike-based information processing models. The system consists of a silicon retina, a PIC...
Shih-Chii Liu, Jörg Kramer, Giacomo Indiveri,...
ET
2007
69views more  ET 2007»
13 years 7 months ago
Oscillator-Based Reconfigurable Sinusoidal Signal Generator for ADC BIST
Abstract In order to perform an on-chip test for characterizing both static and transmission parameters of embedded analog-to-digital converters (ADCs), this paper presents an osci...
Hsin-Wen Ting, Cheng-Wu Lin, Bin-Da Liu, Soon-Jyh ...