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EVOW
2008
Springer
13 years 9 months ago
Analysis of Reconfigurable Logic Blocks for Evolvable Digital Architectures
Abstract. In this paper we propose three small instances of a reconfigurable circuit and analyze their properties using the brute force method and evolutionary algorithm. Although ...
Lukás Sekanina, Petr Mikusek
GECCO
2007
Springer
138views Optimization» more  GECCO 2007»
14 years 1 months ago
Reducing the number of transistors in digital circuits using gate-level evolutionary design
This paper shows that the evolutionary design of digital circuits which is conducted at the gate level is able to produce human-competitive circuits at the transistor level. In ad...
Zbysek Gajda, Lukás Sekanina
SODA
2012
ACM
235views Algorithms» more  SODA 2012»
11 years 10 months ago
Fast zeta transforms for lattices with few irreducibles
We investigate fast algorithms for changing between the standard basis and an orthogonal basis of idempotents for M¨obius algebras of finite lattices. We show that every lattice...
Andreas Björklund, Mikko Koivisto, Thore Husf...
VLSID
2007
IEEE
142views VLSI» more  VLSID 2007»
14 years 8 months ago
Controllability-driven Power Virus Generation for Digital Circuits
The problem of peak power estimation in CMOS circuits is essential for analyzing the reliability and performance of circuits at extreme conditions. The Power Virus problem involves...
K. Najeeb, Karthik Gururaj, V. Kamakoti, Vivekanan...
DAC
1990
ACM
13 years 11 months ago
Timing Verification Using HDTV
In this paper, we provide an overview of a system designed for verifying the consistency of timing specifications for digital circuits. The utility of the system comes from the ne...
Alan R. Martello, Steven P. Levitan, Donald M. Chi...