787 search results - page 70 / 158 » Digital Algebra and Circuits |
ICCD
1993
IEEE
14 years 1 months ago
1993
IEEE
Ravel-XL is a single-boardhardware accelerator for gate-level digital logic simulation. It uses a standard levelizedcode approach to statically schedule gate evaluations.However, u...
ICCAD
2000
IEEE
14 years 18 days ago
2000
IEEE
ct Static timing analysis has traditionally used the PERT method for identifying the critical path of a digital circuit. Due to the influence of the slope of a signal at a particul...
MVA
2007
13 years 10 months ago
2007
Mammography is the best method for early mass detection. In order to limit the search for abnormalities by Computer Aided Diagnosis systems to the region of the breast without und...
EURODAC
1994
IEEE
14 years 1 months ago
1994
IEEE
- The accelerator is destined to circuit-level simulation of digital and analog/digital MOS VLSI'c containing of up to 100 thousand transistors (with 16 Mb RAM host-machine). ...
EH
1999
IEEE
14 years 1 months ago
1999
IEEE
GeneticFPGA is a Java-based tool for evolving digital circuits on Xilinx XC4000EXTM and XC4000XLTM devices. Unlike other FPGA architectures popular with Evolutionary Hardware rese...