47 search results - page 4 / 10 » Digital Circuit Verification Using Partially-Ordered State M... |
FPL
1999
Springer
13 years 12 months ago
1999
Springer
Although verification and simulation tools are always improving, the results they provide remain hard to analyze and interpret. On one hand, verification sticks to the functional ...
CSFW
2011
IEEE
12 years 7 months ago
2011
IEEE
—We present a Horn-clause-based framework for analysing security protocols that use platform configuration registers (PCRs), which are registers for maintaining state inside the...
ATVA
2007
Springer
14 years 1 months ago
2007
Springer
This paper presents a bounded model checking algorithm for the verification of analog and mixed-signal (AMS) circuits using a satisfiability modulo theories (SMT) solver. The sys...
APIN
2002
13 years 7 months ago
2002
This paper describes a new learning by example mechanism and its application for digital circuit design automation. This mechanism uses finite state machines to represent the infer...
ICCAD
2003
IEEE
14 years 4 months ago
2003
IEEE
We have created a stochastic impulse-response (IR) momentextraction algorithm for RC circuit networks. It employs a newly discovered Feynman Sum-over-Paths Postulate. Full paralle...