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» Dimensionality reduction and generalization
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CIKM
2010
Springer
15 years 1 months ago
Fast dimension reduction for document classification based on imprecise spectrum analysis
This paper proposes an algorithm called Imprecise Spectrum Analysis (ISA) to carry out fast dimension reduction for document classification. ISA is designed based on the one-sided...
Hu Guan, Bin Xiao, Jingyu Zhou, Minyi Guo, Tao Yan...
INTERSPEECH
2010
14 years 10 months ago
Multichannel noise reduction using low order RTF estimate
The relative transfer function generalized sidelobe canceler (RTF-GSC) is a popular method for implementing multichannel speech enhancement. However, an accurate estimation of cha...
Subhojit Chakladar, Nam Soo Kim, Yu Gwang Jin, Tae...
DAC
2008
ACM
16 years 4 months ago
Scan chain clustering for test power reduction
An effective technique to save power during scan based test is to switch off unused scan chains. The results obtained with this method strongly depend on the mapping of scan flip-...
Christian G. Zoellin, Hans-Joachim Wunderlich, Jen...
152
Voted
DAC
2003
ACM
16 years 4 months ago
Distributed sleep transistor network for power reduction
Sleep transistors are effective to reduce dynamic and leakage power. The cluster-based design was proposed to reduce the sleep transistor area by clustering gates to minimize the ...
Changbo Long, Lei He
126
Voted
FPGA
2009
ACM
188views FPGA» more  FPGA 2009»
15 years 10 months ago
Clock power reduction for virtex-5 FPGAs
Clock network power in field-programmable gate arrays (FPGAs) is considered and two complementary approaches for clock power reduction in the Xilinx R VirtexTM -5 FPGA are presen...
Qiang Wang, Subodh Gupta, Jason Helge Anderson