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» Dimensions in program synthesis
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ASAP
2007
IEEE
144views Hardware» more  ASAP 2007»
14 years 4 months ago
A High-Throughput Programmable Decoder for LDPC Convolutional Codes
In this paper, we present and analyze a novel decoder architecture for LDPC convolutional codes (LDPCCCs). The proposed architecture enables high throughput and can be programmed ...
Marcel Bimberg, Marcos B. S. Tavares, Emil Mat&uac...
AHS
2006
IEEE
124views Hardware» more  AHS 2006»
14 years 4 months ago
A Generic On-Chip Debugger for Wireless Sensor Networks
— This invited paper overviews the low level debug support hardware required for an on-chip predeployment debugging system for sensor networks. The solution provides significant...
Andrew B. T. Hopkins, Klaus D. McDonald-Maier
DATE
2006
IEEE
108views Hardware» more  DATE 2006»
14 years 4 months ago
Scheduling under resource constraints using dis-equations
Scheduling is an important step in high-level synthesis (HLS). In our tool, we perform scheduling in two steps: coarse-grain scheduling, in which we take into account the whole co...
Hadda Cherroun, Alain Darte, Paul Feautrier
ECBS
2006
IEEE
166views Hardware» more  ECBS 2006»
14 years 4 months ago
Model Transformations in the Model-Based Development of Real-time Systems
In this paper we argue for UML-based metamodeling and pattern-based graph transformation techniques in computer-based systems development through an illustrative example from the ...
Tivadar Szemethy, Gabor Karsai, Daniel Balasubrama...
ACSD
2005
IEEE
162views Hardware» more  ACSD 2005»
14 years 3 months ago
Complexity Results for Checking Distributed Implementability
We consider the distributed implementability problem as: Given a labeled transition system TS together with a distribution ∆ of its actions over a set of processes, does there ex...
Keijo Heljanko, Alin Stefanescu