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» Dimensions in program synthesis
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ISSS
2002
IEEE
151views Hardware» more  ISSS 2002»
14 years 2 months ago
Tuning of Loop Cache Architectures to Programs in Embedded System Design
Adding a small loop cache to a microprocessor has been shown to reduce average instruction fetch energy for various sets of embedded system applications. With the advent of core-b...
Frank Vahid, Susan Cotterell
MPC
1989
Springer
76views Mathematics» more  MPC 1989»
14 years 1 months ago
The Projection of Systolic Programs
A scheme is presented which transforms systolic programs with a two-dimensionalstructure to one dimension. The elementary steps of the transformation are justified by theorems in ...
Christian Lengauer, Jeff W. Sanders
FPGA
2011
ACM
401views FPGA» more  FPGA 2011»
13 years 1 months ago
LegUp: high-level synthesis for FPGA-based processor/accelerator systems
In this paper, we introduce a new open source high-level synthesis tool called LegUp that allows software techniques to be used for hardware design. LegUp accepts a standard C pro...
Andrew Canis, Jongsok Choi, Mark Aldham, Victor Zh...
EUROPAR
2003
Springer
14 years 3 months ago
KOJAK - A Tool Set for Automatic Performance Analysis of Parallel Programs
Abstract. Today’s parallel computers with SMP nodes provide both multithreading and message passing as their modes of parallel execution. As a consequence, performance analysis a...
Bernd Mohr, Felix Wolf
CHARME
2001
Springer
98views Hardware» more  CHARME 2001»
14 years 2 months ago
Hardware Synthesis Using SAFL and Application to Processor Design
Abstract. We survey the work done so far in the FLaSH project (Functional Languages for Synthesising Hardware) in which the core ideas are (i) using a functional language SAFL to d...
Alan Mycroft, Richard Sharp