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SPAA
2004
ACM
14 years 2 months ago
Cache-oblivious shortest paths in graphs using buffer heap
We present the Buffer Heap (BH), a cache-oblivious priority queue that supports Delete-Min, Delete, and Decrease-Key operations in O( 1 B log2 N B ) amortized block transfers fro...
Rezaul Alam Chowdhury, Vijaya Ramachandran
MICRO
2009
IEEE
124views Hardware» more  MICRO 2009»
14 years 3 months ago
ZerehCache: armoring cache architectures in high defect density technologies
Aggressive technology scaling to 45nm and below introduces serious reliability challenges to the design of microprocessors. Large SRAM structures used for caches are particularly ...
Amin Ansari, Shantanu Gupta, Shuguang Feng, Scott ...
UIST
2004
ACM
14 years 2 months ago
SketchREAD: a multi-domain sketch recognition engine
We present SketchREAD, a multi-domain sketch recognition engine capable of recognizing freely hand-drawn diagrammatic sketches. Current computer sketch recognition systems are dif...
Christine Alvarado, Randall Davis
GIS
2006
ACM
14 years 10 months ago
Efficient GML-native processors for web-based GIS: techniques and tools
Geography Markup Language (GML) is an XML-based language for the markup, storage, and exchange of geospatial data. It provides a rich geospatial vocabulary and allows flexible doc...
Chia-Hsin Huang, Tyng-Ruey Chuang, Dong-Po Deng, H...
IESS
2007
Springer
120views Hardware» more  IESS 2007»
14 years 3 months ago
Error Containment in the Time-Triggered System-On-a-Chip Architecture
Abstract: The time-triggered System-on-a-Chip (SoC) architecture provides a generic multicore system platform for a family of composable and dependable giga-scale SoCs. It supports...
Roman Obermaisser, Hermann Kopetz, Christian El Sa...