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CGO
2010
IEEE
14 years 2 months ago
Automatic creation of tile size selection models
Tiling is a widely used loop transformation for exposing/exploiting parallelism and data locality. Effective use of tiling requires selection and tuning of the tile sizes. This is...
Tomofumi Yuki, Lakshminarayanan Renganarayanan, Sa...
ISPD
2010
ACM
195views Hardware» more  ISPD 2010»
14 years 2 months ago
Density gradient minimization with coupling-constrained dummy fill for CMP control
In the nanometer IC design, dummy fill is often performed to improve layout pattern uniformity and the post-CMP quality. However, filling dummies might greatly increase intercon...
Huang-Yu Chen, Szu-Jui Chou, Yao-Wen Chang
ICS
2009
Tsinghua U.
14 years 2 months ago
High-performance regular expression scanning on the Cell/B.E. processor
Matching regular expressions (regexps) is a very common workload. For example, tokenization, which consists of recognizing words or keywords in a character stream, appears in ever...
Daniele Paolo Scarpazza, Gregory F. Russell
CODES
2005
IEEE
14 years 1 months ago
Aggregating processor free time for energy reduction
Even after carefully tuning the memory characteristics to the application properties and the processor speed, during the execution of real applications there are times when the pr...
Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, ...
GECCO
2009
Springer
193views Optimization» more  GECCO 2009»
14 years 4 days ago
Optimization of dynamic memory managers for embedded systems using grammatical evolution
New portable consumer embedded devices must execute multimedia applications (e.g., 3D games, video players and signal processing software, etc.) that demand extensive memory acces...
José L. Risco-Martín, David Atienza,...