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CLUSTER
2008
IEEE
14 years 2 months ago
Context-aware address translation for high performance SMP cluster system
—User-level communication allows an application process to access the network interface directly. Bypassing the kernel requires that a user process accesses the network interface...
Moon-Sang Lee, Joonwon Lee, Seungryoul Maeng
IEEEPACT
2006
IEEE
14 years 2 months ago
Branch predictor guided instruction decoding
Fast instruction decoding is a challenge for the design of CISC microprocessors. A well-known solution to overcome this problem is using a trace cache. It stores and fetches alrea...
Oliverio J. Santana, Ayose Falcón, Alex Ram...
ICPP
2002
IEEE
14 years 1 months ago
Out-of-Order Instruction Fetch Using Multiple Sequencers
Conventional instruction fetch mechanisms fetch contiguous blocks of instructions in each cycle. They are difficult to scale since taken branches make it hard to increase the siz...
Paramjit S. Oberoi, Gurindar S. Sohi
OSDI
1994
ACM
13 years 9 months ago
Opportunistic Log: Efficient Installation Reads in a Reliable Storage Server
In a distributed storage system, client caches managed on the basis of small granularity objects can provide better memory utilization then page-based caches. However, object serv...
James O'Toole, Liuba Shrira
MICRO
2006
IEEE
113views Hardware» more  MICRO 2006»
13 years 8 months ago
Exploiting Fine-Grained Data Parallelism with Chip Multiprocessors and Fast Barriers
We examine the ability of CMPs, due to their lower onchip communication latencies, to exploit data parallelism at inner-loop granularities similar to that commonly targeted by vec...
Jack Sampson, Rubén González, Jean-F...