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ICCD
2004
IEEE
129views Hardware» more  ICCD 2004»
14 years 4 months ago
Cache Array Architecture Optimization at Deep Submicron Technologies
A cache access time model, PRACTICS (PRedictor of Access and Cycle TIme for Cache Stack), has been developed to optimize the memory array architecture for the minimum access and c...
Annie (Yujuan) Zeng, Kenneth Rose, Ronald J. Gutma...
ICIP
2005
IEEE
14 years 9 months ago
A likelihood function for block-based motion analysis
In this paper, the computation of likelihood of block motion candidates is considered. The method is based on the evaluation of the sum of squared differences (SSD) measure for lo...
Janne Heikkilä, Olli Silvén, Pekka San...
IJIPT
2008
114views more  IJIPT 2008»
13 years 7 months ago
Enabling global multimedia distributed services based on hierarchical DHT overlay networks
The provision of innovating multimedia services is a high priority for service providers. Due to the the high traffic volume characteristics of multimedia content, decentralised s...
Isaías Martinez-Yelmo, Alex Bikfalvi, Carme...
CSREAESA
2004
13 years 9 months ago
A Distributed FIFO Scheme for System on Chip Inter-Component Communication
Interconnect delays are increasingly becoming the dominant source of performance degradation in the nano-meter regime, largely because the wires do not scale as fast as the device...
Ray Robert Rydberg III, Jabulani Nyathi, Jos&eacut...
ISCAS
2005
IEEE
126views Hardware» more  ISCAS 2005»
14 years 1 months ago
A distributed FIFO scheme for on chip communication
— Interconnect delays are increasingly becoming the dominant source of performance degradation in the nano-meter regime, largely because of disturbances that result from parasiti...
Ray Robert Rydberg III, Jabulani Nyathi, Jos&eacut...