A Distributed FIFO Scheme for System on Chip Inter-Component Communication

Interconnect delays are increasingly becoming the dominant source of performance degradation in the nano-meter regime, largely because the wires do not scale as fast as the devices. Scaling implies that complete systems can now be built on a single chip, requiring long interconnects for global signals and clock distribution networks. We propose having distributed first in first out buffers to facilitate communication between components/modules of highly integrated systems, such as system on chip. Using first in first out buffers will alleviate the clock skew, clock distribution and single clock synchronization problems; all of which are a result of global interconnect delays. In this paper, we present simple buffer circuitry and the associated control circuits that

• Type: Conference
• Year: 2004
• Where: CSREAESA
• Authors: Ray Robert Rydberg III, Jabulani Nyathi, José G. Delgado-Frias
• Keywords: Clock Distribution, Clock Distribution Networks, CSREAESA 2004, CSREAESA 2007, Interconnect Delays