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TCAD
2008
136views more  TCAD 2008»
13 years 7 months ago
A Geometric Programming-Based Worst Case Gate Sizing Method Incorporating Spatial Correlation
We present an efficient optimization scheme for gate sizing in the presence of process variations. Our method is a worst-case design scheme, but it reduces the pessimism involved i...
Jaskirat Singh, Zhi-Quan Luo, Sachin S. Sapatnekar
PEPM
2009
ACM
15 years 8 months ago
Static Consistency Checking for Verilog Wire Interconnects
The Verilog hardware description language has padding semantics that allow designers to write descriptions where wires of different bit widths can be interconnected. However, many ...
Cherif Salama, Gregory Malecha, Walid Taha, Jim Gr...
POPL
2010
ACM
14 years 5 months ago
From Program Verification to Program Synthesis
This paper describes a novel technique for the synthesis of imperative programs. Automated program synthesis has the potential to make programming and the design of systems easier...
Saurabh Srivastava, Sumit Gulwani, Jeffrey S. Fost...
ISPD
2004
ACM
97views Hardware» more  ISPD 2004»
14 years 1 months ago
Implementation and extensibility of an analytic placer
Automated cell placement is a critical problem in VLSI physical design. New analytical placement methods that simultaneously spread cells and optimize wirelength have recently rec...
Andrew B. Kahng, Qinke Wang
TWC
2008
120views more  TWC 2008»
13 years 7 months ago
Binary Power Control for Sum Rate Maximization over Multiple Interfering Links
We consider allocating the transmit powers for a wireless multi-link (N-link) system, in order to maximize the total system throughput under interference and noise impairments, and...
Anders Gjendemsjø, David Gesbert, Geir E. &...