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IPPS
2007
IEEE
14 years 3 months ago
Load Miss Prediction - Exploiting Power Performance Trade-offs
— Modern CPUs operate at GHz frequencies, but the latencies of memory accesses are still relatively large, in the order of hundreds of cycles. Deeper cache hierarchies with large...
Konrad Malkowski, Greg M. Link, Padma Raghavan, Ma...
DSD
2009
IEEE
136views Hardware» more  DSD 2009»
14 years 28 days ago
An Evaluation of Behaviors of S-NUCA CMPs Running Scientific Workload
Modern systems are able to put two or more processors on the same die (Chip Multiprocessors, CMP), each with its private caches, while the last level caches can be either private ...
Pierfrancesco Foglia, Francesco Panicucci, Cosimo ...
TIT
2008
129views more  TIT 2008»
13 years 9 months ago
Cooperative Fading Regions for Decode and Forward Relaying
Abstract--Cooperative transmission protocols over fading channels are based on a number of relaying nodes to form virtual multiantenna transmissions. Diversity provided by these te...
Stefano Savazzi, Umberto Spagnolini
CLUSTER
2002
IEEE
14 years 2 months ago
Mixed Mode Matrix Multiplication
In modern clustering environments where the memory hierarchy has many layers (distributed memory, shared memory layer, cache,  ¡ ¢  ), an important question is how to fully u...
Meng-Shiou Wu, Srinivas Aluru, Ricky A. Kendall
IPPS
2007
IEEE
14 years 3 months ago
Performance Analysis of a Family of WHT Algorithms
This paper explores the correlation of instruction counts and cache misses to runtime performance for a large family of divide and conquer algorithms to compute the Walsh–Hadama...
Michael Andrews, Jeremy Johnson