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ISPASS
2010
IEEE
14 years 4 months ago
Performance-effective operation below Vcc-min
Continuous circuit miniaturization and increased process variability point to a future with diminishing returns from dynamic voltage scaling. Operation below Vcc-min has been prop...
Nikolas Ladas, Yiannakis Sazeides, Veerle Desmet
IPPS
2003
IEEE
14 years 2 months ago
Using Incorrect Speculation to Prefetch Data in a Concurrent Multithreaded Processor
Concurrent multithreaded architectures exploit both instruction-level and thread-level parallelism through a combination of branch prediction and thread-level control speculation. ...
Ying Chen, Resit Sendag, David J. Lilja
IPPS
2003
IEEE
14 years 2 months ago
Miss Penalty Reduction Using Bundled Capacity Prefetching in Multiprocessors
While prefetch has proven itself useful for reducing cache misses in multiprocessors, traffic is often increased due to extra unused prefetch data. Prefetching in multiprocessors...
Dan Wallin, Erik Hagersten
IPPS
2002
IEEE
14 years 2 months ago
Improving Performance of Multiple Sequence Alignment Analysis in Multi-Client Environments
This paper is concerned with the efficient execution of multiplesequence alignmentmethodsin a multipleclientenvironment. Multiple sequence alignment (MSA) is a computationally ex...
Ümit V. Çatalyürek, Eric Stahlber...
HPCC
2009
Springer
14 years 1 months ago
A Quantitative Study of Memory System Interference in Chip Multiprocessor Architectures
—The potential for destructive interference between running processes is increased as Chip Multiprocessors (CMPs) share more on-chip resources. We believe that understanding the ...
Magnus Jahre, Marius Grannæs, Lasse Natvig