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ISHPC
1999
Springer
14 years 1 months ago
Utilization of Cache Area in On-Chip Multiprocessor
On-chip multiprocessor can be an alternative to the wide-issue superscalar processor approach which is currently the mainstream to exploit the increasing number of transistors on ...
Hitoshi Oi, N. Ranganathan
ICS
2009
Tsinghua U.
14 years 3 months ago
Zero-content augmented caches
It has been observed that some applications manipulate large amounts of null data. Moreover these zero data often exhibit high spatial locality. On some applications more than 20%...
Julien Dusser, Thomas Piquet, André Seznec
ICS
2005
Tsinghua U.
14 years 2 months ago
A NUCA substrate for flexible CMP cache sharing
We propose an organization for the on-chip memory system of a chip multiprocessor, in which 16 processors share a 16MB pool of 256 L2 cache banks. The L2 cache is organized as a n...
Jaehyuk Huh, Changkyu Kim, Hazim Shafi, Lixin Zhan...
GCC
2003
Springer
14 years 2 months ago
Research and Design of Remote Education System Based on CSCW
Guided by the cooperation theory, this paper puts forward an interactive and cooperative learning environment design that is based on the self-learning mode and cooperative learnin...
Chunzhi Wang, Miao Shao, Jing Xia, Huachao Chen
HPCA
2005
IEEE
14 years 9 months ago
Effective Instruction Prefetching in Chip Multiprocessors for Modern Commercial Applications
In this paper, we study the instruction cache miss behavior of four modern commercial applications (a database workload, TPC-W, SPECjAppServer2002 and SPECweb99). These applicatio...
Lawrence Spracklen, Yuan Chou, Santosh G. Abraham